This invention generally relates to processes for forming semiconductor device integrated circuits including MOSFET devices and more particularly to a pair of MOSFET devices having opposite polarity and enhanced device performance provided by selectively forming an offset spacer portion and a strained L-shaped spacer portion which have the benefits of controlling a desired strain on the channel region as well as protecting high-K gate dielectrics from sub-oxide formation under gate edge region.
As MOSFET device feature sizes are scaled below 0.25 microns including below 0.1 micron, new methods have been proposed for forming and more precisely locating offset spacers to aid in forming doped regions producing MOSFETs having better short channel effect and desired device characteristics, for example reducing short channel effects (SCE) such that we can get better threshold voltage (VT) roll-off, drain induced barrier lowering (DIBL), and subthreshold swing variation.
There is therefore a continuing need in the semiconductor device integrated circuit manufacturing art for improved spacers and methods for forming the same to improve device performance regardless of device polarity. Also, in a high-K device, oxygen may diffuse into a high-K dielectric layer and forms a sub-oxide layer, thereby degrading performances thereof.
It is therefore an object of the present invention to provide an offset and a strained L-shaped spacers, and methods for forming the same to improve device performance regardless of device polarity and to protect sub-oxide formation, while overcoming other shortcomings of the prior art.